The present invention relates to an operational amplifier or a comparator, and more particularly to a circuit which can improve the slew rate (the response speed of an output signal as a function of an input signal) of the operational amplifier having a capacitive load at an output terminal.
Most electronic circuits use an operational amplifier or the comparator which produces an output signal, by summing, subtracting or differential amplifying input signals of an invert terminal and a non-inverted terminal. In such an operational amplifier, the response of the output signal as a function of an input signal is important to the performance and reliability of the electronic circuit. Specially, if a comparator used in a semiconductor memory device has a slow response speed, the malfunction of the memory device operating at a high speed as well as a slow data access time will result.
FIG. 1 is a circuit diagram illustrating a comparator (or an operational amplifier) of the prior art. As shown in FIG. 1, it will be appreciated that the comparator and the differential amplifier of an N-channel input type are the same in construction. Therefore, when the potential of a first input terminal 21 is higher than that of a second input terminal 22, P type MOS transistors 4 and 5 and N type MOS transistors 7 and 11 are turned on to drop the potential of a second output terminal 24. If the potential of the second input terminal 22 is higher the first input terminal 21, a power supply voltage V.sub.DD is charged on the second output terminal 24 through a P type MOS transistor 10. In this case, the voltage gain A.sub.VO1 of a first output terminal 23 and the voltage gain A.sub.VO2 of the second output terminal 24 are calculated respectively as follows. EQU A.sub.VO1 =gm.sub.2 /gm.sub.6 EQU A.sub.VO2 ={gm.sub.1 (S.sub.10 /S.sub.6)}/(gds.sub.10 +gds.sub.11)
Wherein gm.sub.1, gm.sub.2 and gm.sub.6 are the transconductance of N type MOS transistors 1 and 2 and P type MOS transistor 6, respectively, gds the channel conductance, S the ratio of the width of channel to the length thereof.
In case that the output voltage V.sub.OUT is increased, the slew rate SR at the second output terminal 24 becomes maximum value when the pull-down current I.sub.11 flowing into a ground voltage terminal V.sub.SS from the second output terminal 24, through the N type MOS transistor 11, is "0". In case that the output voltage is decreased, the slew rate SR at the second output terminal 24 becomes maximum value when the pull-up current I.sub.10 flowing into the second output terminal 24 from the power supply voltage terminal V.sub.DD, through the P type MOS transistor 10, is "0".
However, at the second output terminal 24, there exists the load capacitance C.sub.L resulting from parasitic capacitor 15, which makes the load current i.sub.L flow. The load capacitance C.sub.L and the load current i.sub.L have an important effect on the slew rate SR during the potential of the second output terminal 24 is changed from logic "LOW" to logic "HIGH" or from logic "HIGH" to logic "LOW". In detail, the slew rate SR is defined as the differential coefficient of the output voltage V.sub.out with respect to time, and on the other hand the load current i.sub.L indicates the value the pull-down current I.sub.11 from the pull-up current I.sub.10. Thus, the slew rate SR can be expressed as follows. EQU SR=.vertline.dV.sub.out /dt.vertline.=.vertline.i.sub.L /C.sub.L .vertline.=.vertline.(I.sub.10 -I.sub.11)/C.sub.L .vertline.
As shown in the above expression concerning the slew rate SR, in order to increase the slew rate SR (or to have fast response speed of an output signal as a function of an input signal), the load capacitance C.sub.L should be decreased or the load current i.sub.L should be increased. The value of the load capacitance C.sub.L can not be changed because the load capacitance, as a parasitic element, has a inevitably fixed value in a circuit construction, but it is possible to increase the load current i.sub.L by increasing the size of P type MOS transistor 10 and N type MOS transistor 11. However, to increase the size of MOS transistors 10 and 11 for use in output results undesirably in the increase of power consumption of the circuit.